1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of cutting gate structures on transistor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar transistor devices, FinFET transistor devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region. In addition to transistors, which is an example of an active circuit element or semiconductor device, an integrated circuit product also includes passive circuit elements such as, for example, resistors, capacitors, etc.
For many FET devices, the gate structures are initially formed as continuous line-type structures that extend across the entire substrate, including across both active regions and isolation regions. These gate structures may be final gate structures for the FET devices (a so-called “gate-first” manufacturing technique) or they may be sacrificial gate structures when the final gate structures for the FET devices are formed using replacement gate manufacturing techniques. The long continuous line-type gate structures are formed by depositing the materials for the gate structures across the entire substrate, forming a patterned gate etch mask above the deposited gate materials and performing one or more etching processes through the patterned gate etch mask to remove the exposed portions of the gate materials. At that point, a spacer structure will be formed adjacent the long continuous line-type gate structures. At some point after other processing has occurred, e.g., formation of epi material in the source/drain regions of the devices, portions of the long continuous line-type gate structures will be removed or “cut” so as to define remaining portions or segments of the original long continuous line-type gate structures, wherein the segments will function as final gate structure (gate-first technique) or sacrificial gate structures (replacement gate technique).
FIGS. 1A-1C depict some problems that may be encountered when performing at least one prior art gate-cut processing technique. Depicted therein are three illustrative gate structures 10A-10C wherein it is desired to remove or “cut” a portion of the middle gate 10B. FIG. 1C is a cross-sectional view showing the three gates 10A-C positioned above an isolation region 16 defined in the substrate 14. Also depicted are illustrative gate structures 20 (comprised of a gate insulation layer and a gate electrode layer), sidewall spacers 21, gate caps 22, a layer of insulating material 18 and a patterned “gate cut” masking layer 24 with an opening 24A defined therein. FIG. 1A depicts the situation wherein the opening 24A is perfectly aligned over the middle gate 10B, i.e., the opening 24A does not expose any portion of the adjacent gate structures 10A or 10C. However, as gate pitch dimensions are continuously decreasing, it is very difficult and expensive to achieve the perfect alignment of the gate cut mask 24 as depicted in FIG. 1A, i.e., there is a very small process window for properly positioning the opening 24A in the gate cut mask 24 at the desired location. As shown in FIG. 1B, in some cases, due to a variety of factors, the opening 24A in the gate cut mask 24 is misaligned such that the opening 24A exposes a portion of an adjacent gate structure, i.e., the gate structure 10A. FIG. 1C is a cross-sectional view depicting the product wherein the gate cut mask 24 is misaligned (as depicted in FIG. 1B) after an etching process was performed to remove the portions of the gate 10B exposed by the gate cut mask 24, thereby defining an opening 26 where the gate 10B was cut. Due to the misalignment of the gate cut mask 24, the gate cap 22 on the gate 10A and the gate structure 20 on the gate 10A may also be attacked during the etching process, as depicted in the dashed line region 28. If the gate structure 20 on the gate 10A is subjected to significant attack, significant gouging, the gate structure 20 may not work for its intended purpose, or at least not as well as intended, and production yields may suffer. Some prior art techniques that have been performed in an attempt to prevent gouging of the gate structure 20 of the gate 10A have included forming a separate silicon nitride structure (not shown)—sometimes referred to as a “divot-fill” in the space adjacent the partially removed gate cap 22 and above the gate structure 20 prior to performing the etching process to remove the gate structure 20 from the gate 10B. Such additional processing steps are time-consuming and expensive.
The present disclosure is directed to various methods of cutting gate structures on transistor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.